A) Field of the Invention
The present invention relates to a solid state imaging unit and an endoscope using the solid state imaging unit.
B) Description of the Related Art
FIG. 5A is a block diagram showing a main portion of a solid image pickup device assembling a solid state imaging unit, and FIGS. 5B and 5C are schematic plan views showing the structure of a solid state imaging unit. FIG. 5D is a cross sectional view briefly showing a portion of a light reception portion of a solid state imaging unit.
Referring to FIG. 5A, the structure of a solid state image pickup device will be described. A solid state imaging unit 51 generates signal charges corresponding to an amount of light incident upon each pixel and supplies an image signal corresponding to the generated signal charges. A drive signal generator 52 generates drive signals (transfer voltage, etc.) for driving the solid state imaging unit 51 and supplies them to the solid state imaging unit 51. An analog front end (AFE) 53 performs correlation double sampling of an output signal of the solid state imaging unit 51, amplifies the sampled signal at an externally set gain, performs analog-digital conversion and outputs a digital signal. A digital signal processor (DSP) 54 processes an image signal supplied from the analog front end 53, such as recognition process, data compression and network control, and outputs the processed image data. A timing generator (TG) 55 generates timing signals for the solid state imaging unit 51, drive signal generator 52 and analog front end 53, to control the operations thereof.
Solid state imaging units are mainly divided into CCD types and MOS types. In the CCD type, charges generated in a pixel is transferred by charge coupled devices (CCD). In the MOS type, charges generated in a pixel are amplified by a MOS transistor and output. Although not limitative, the following description will be made by using a CCD type as an example.
The drive signal generator 52 includes, for example, a V driver for generating a vertical CCD drive signal. Signals supplied from the drive signal generator 52 to the solid state imaging unit 51 are a horizontal CCD drive signal, a vertical CCD drive signal, an output amplifier drive signal and a substrate bias signal.
As shown in FIG. 5B, the solid state imaging unit is constituted of: a plurality of photosensitive units 62 disposed, for example, in a matrix shape; a plurality of vertical CCD units 64, a horizontal CCD unit 66 electrically connected to the vertical CCD units 64; and an amplifier circuit unit 67, connected to an output terminal of the horizontal CCD unit 66, for amplifying an output charge signal from the horizontal CCD unit 66. A light reception portion (pixel arrangement unit) 61 is constituted of the photosensitive units 62 and vertical CCD units 64.
The photosensitive unit 62 is constituted of a photosensitive element, e.g., a photoelectric conversion element (photodiode) and a read out gate. The photoelectric conversion element generates signal charges corresponding to an incidence light amount and accumulates them. The accumulated signal charges are read via the read out gate to the vertical CCD unit 64 and transferred in the vertical CCD unit (vertical transfer channel) 64 as a whole toward the horizontal CCD unit 66 (in a vertical direction). Signal charges transferred to the bottom end of the vertical CCD unit 64 are transferred in the horizontal CCD unit (horizontal transfer channel) 66 as a whole in a direction crossing a vertical direction, e.g., in a horizontal direction (a direction perpendicular to a vertical direction), and thereafter converted into a voltage signal. The voltage signal is applied to an amplifier 67, amplified and output.
The photosensitive units 62 are disposed in a square matrix layout at a constant pitch in the row and column directions as shown in FIG. 5B, or disposed in a honeycomb layout in the row and column directions by shifting every second units, for example, by a half pitch.
FIG. 5C is a schematic plan view of a solid state imaging unit having the pixel interleaved layout. The pixel interleaved layout has photosensitive units 62 disposed in a first square matrix layout and photosensitive units 62 disposed in a second square matrix layout at positions between lattice points of the first square matrix layout. Vertical CCD units (vertical transfer channels) 64 are disposed in a zigzag way between photosensitive units 62. Also in this case, signal charges are transferred in the vertical transfer channel as a whole in a direction (vertical direction) toward the horizontal CCD unit 66. Although this layout is called a pixel interleaved layout, the photosensitive unit 62 of most pixel interleaved layouts is octangular.
As shown in FIG. 5D, formed in a p-type well 82 formed in a semiconductor substrate 81, e.g., an n-type silicon substrate, are a photoelectric conversion element 71 made of an n-type impurity doped region, a p-type read gate 72 disposed next to the photoelectric conversion element 71, and a vertical transfer channel 73 of made of an n-type region disposed next to the read gate 72. A vertical transfer electrode 75 is formed above the vertical transfer channel 73, with a gate insulating film 74 being interposed therebetween. A p-type channel stop region 76 is formed between adjacent photoelectric conversion elements 71.
The channel stop region 76 is used for electrically isolating the photoelectric conversion elements 71, vertical transfer channels 73 and the like. The gate insulating film 74 is a silicon oxide film formed on the surface of the semiconductor substrate 81, for example, by thermal oxidation. The vertical transfer electrode 75 is constituted of first and second vertical transfer electrodes made of, for example, polysilicon. The first and second vertical transfer electrodes may be made of amorphous silicon. An insulating silicon oxide film 77 is formed on the vertical transfer electrode 75, for example, by thermally oxidizing polysilicon. The vertical CCD unit 64 is constituted of the vertical transfer channel 73, upper gate insulating film 74 and vertical transfer electrode 75. The horizontal CCD unit 66 is constituted of a horizontal transfer channel, upper gate insulating film and horizontal transfer electrode.
A light shielding film 79 of, e.g., tungsten, is formed above the vertical transfer electrode 75, with the insulating silicon oxide film 77 being interposed therebetween. Openings 79a are formed through the light shielding film 79 at positions above the photoelectric conversion elements 71. A silicon nitride film 78 is formed on the light shielding film 79. The silicon nitride film 78 is not necessarily required.
Signal charges corresponding to an incidence light amount generated in the photoelectric conversion element 71 are read via the read out gate 72 into the vertical transfer channel 73 and transferred in the vertical transfer channel 73 in response to a drive signal (transfer voltage) applied to the vertical transfer electrodes 75. As described above, the light shielding film 79 has the openings 79a above the photoelectric conversion elements 71 and prevents light incident upon the light reception portion 61 from entering the region other than the photoelectric conversion elements 71.
A planarized layer 83a made of, e.g., borophosphosilicate glass (BPSG) is formed above the light shielding film 79. On this planarized surface, a color filter layer 84 is formed which is three primary colors: red (R), green (G) and blue (B). Another planarized layer 83b is formed on the color filter layer 84. On the planarized layer 83 having a planarized surface, micro lenses 85 are formed, for example, by melting and solidifying a photoresist pattern of micro lenses. Each micro lens 85 is a fine hemispherical convex lens disposed above each photoelectric conversion element 71. The micro lens 85 converges incidence light to the photoelectric conversion elements 71. Light converged by one micro lens 85 passes through the color filter layer 84 of one of the red (R), green (G) and blue (B) and becomes incident upon one photoelectric conversion element 71. Therefore, the photoelectric conversion elements include three types of photoelectric conversion elements: photoelectric conversion elements upon which light passed through the red (R) color filter layer 84 becomes incident; photoelectric conversion elements upon which light passed through the green (G) color filter layer 84 becomes incident; and photoelectric conversion elements upon which light passed through the blue (B) color filter layer 84 becomes incident.
In the specification and claims, “above” the photoelectric conversion element or the semiconductor substrate on which the photoelectric conversion elements are formed, intended to mean “at a higher position” in the above-described structure of the solid state imaging unit.
FIG. 6 is a schematic plan view of a semiconductor chip 23 formed with the solid state imaging unit shown in FIG. 5B or 5C. The semiconductor chip 23 includes, in addition to the solid state imaging unit shown in FIG. 5B or 5C, a protective circuit 70, a spacer (a support member) 68, a protective glass (protective member) 69 and a plurality of pads 24a. A horizontal transfer channel 66a, a horizontal transfer channel output port 66b and a floating diffusion region 66c shown in FIG. 6 are elements constituting the horizontal CCD unit 66 shown in FIG. 5B or 5C.
The protective circuit 70 is used for mitigating unfavorable events in the solid state imaging unit. The spacer 68 is formed on the principal surface of a semiconductor substrate formed with photoelectric conversion elements, surrounding as viewed in plan the solid state imaging unit. A thickness of the spacer 68 is, e.g., 100 μm. The spacer 68 is adhered to the surface of the semiconductor substrate, for example, with adhesive. On the spacer 68, the protective glass 69 of transparent material is placed which has a thickness of, e.g., 250 μm.
The protective glass 69 protects the solid state imaging unit from moisture and mechanical factors which might damage the solid state imaging unit. The semiconductor chip 23 is manufactured by forming a number of solid state imaging units on a silicon wafer and dicing each solid state imaging unit. The protective glass 69 can prevent dust, which is formed during the manufacture processes, mainly the dicing process and subsequent processes, from attaching the light reception portion 61. One of mount processes is a sealing process of sealing the solid state imaging unit by the spacer 68 and protective glass 69.
The pads 24a are external interconnection terminals for electrical connection between the semiconductor chip 23 and a wiring board formed with a driver circuit and the like and wirings. This electrical connection will be later described.
Signal charges generated and accumulated in the light reception portion (pixel arrangement unit) 61 are transferred to the horizontal transfer channel 66a in the manner described earlier, and transferred in the horizontal transfer channel 66a toward the horizontal transfer channel output port 66b and arrive at the floating diffusion region 66c. The signal charges are converted into a voltage at the floating diffusion region 66c, and the converted voltage is sent to an amplifier 67 whereat the voltage signal is amplified and output to an external.
The size of each pixel of a solid state imaging unit including CCDs is reduced as a number of pixels are used. This size reduction makes smaller the size of an effective light reception portion of pixels. On-chip micro lenses are used widely in order to improve an effective aperture ratio of each pixel.
A solid state image pickup device mounting compact micro lenses is disclosed (for example, refer to Japanese Patent Laid-open Publication No. HEI-7-202152), in which a sealing member made of transparent material and integrally forming a frame on a bottom border area thereof is disposed only on a light reception portion of a solid state imaging unit chip with the micro lenses, and the solid state imaging unit and the sealing member are hermetically sealed with a space of 5 μm or broader being formed between the surface of the micro lenses and the bottom surface of the sealing member.
A method is disclosed for manufacturing a solid state image pickup device capable of being manufactured with ease and at high reliability while the needs for compactness are met (for example, refer to Japanese Patent Laid-open Publication No. 2004-6834).
In the solid state imaging unit whose protective glass 69 is disposed above the semiconductor chip 23 by using the spacer 68, it is desired to adhere the spacer 68 to the semiconductor chip 23 near at the light reception portion 61 of the solid state imaging unit, in order to make compact the semiconductor chip 23 and hence the solid state image pickup device.
As described above, when the spacer 68 is mounted on the semiconductor chip 23, adhesive is used. In this case, the adhesive may protrude to the inner space of the spacer 68.
The semiconductor chip 23 formed with the solid state imaging unit has unfavorable areas if the spacer 68 is mounted and adhesive is attached in these areas. The unfavorable areas if adhesive is attached in these areas, are the upper areas of the horizontal transfer channel 66a, floating diffusion region 66c and amplifier 67, among other areas.
One of the reasons that attachment of adhesion is not preferable, is a change in capacitive components to be caused by the attachment of adhesion and hence a change in electronical characteristics. For example, if adhesion is attached to the floating diffusion region 66c having an electronical capacitance of 10 to 100 fF and the electrical capacitance of only several fF changes, the electrical characteristics are influenced considerably.
The second reason that attachment of adhesion is not preferable, is that electric charges may be mixed in an adhesive layer. Adhesive contains often organic dielectric and charges with polarization may be mixed in the dielectric. For example, the floating diffusion region 66c performs a charge-voltage conversion for transferred signal charges so that it is sensitive to charges as well as capacitive components and prone to a change in the characteristics by charges. It is therefore preferable to avoid attachment of adhesive.
It is therefore preferable to mount the semiconductor chip 23 by setting the spacer 68 away from the upper areas of the horizontal transfer channel 66a, floating diffusion region 66c and amplifier 67.
Some width of the spacer 68 is required in order to adhere securely the spacer 68 to the semiconductor chip 23. Although it is possible to partially narrow the width of the spacer 68, this is not preferable because an adhesion force in the narrow area becomes weak and the sealing performance in this narrow area may be degraded.
Reverting to FIG. 6, as the horizontal transfer channel 66a, floating diffusion region 66c and amplifier 67 are disposed in the layout shown, the amplifier 67 positions lower left of the light reception portion 61 and along the left side of the semiconductor chip 23. In order to make compact the semiconductor chip 23, the spacer 68 is placed traversing the upper area of the amplifier 67. However, since it is not preferable to adhere the spacer 68 to the semiconductor chip 23 in the upper area (the surface of the semiconductor chip 23) of the amplifier 67, the spacer 68 partially removing a portion which contacts this upper area is adhered to the surface of the semiconductor chip 23. In FIG. 6, the removed portion is indicated by a one-dot chain line. It is necessary for the removed portion to have a remaining width necessary for secure adhesion.
With this arrangement that the spacer 68 with the removed portion in contact with the upper area of the amplifier 67 is adhered and the protective glass 69 is placed on the spacer, it has been found unsatisfactory, however, in that the adhesion between the narrowed area of the spacer 68 and the semiconductor chip 23 is not good and a sufficient sealing performance may become difficult to obtain.
Since the spacer 68 with the four side is integrally molded, the sealing performance is not degraded by the reason of the structure of the spacer 68 itself. Even if the spacer is not integrally molded, the sealing performance can be retained by using adhesive or the like.